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never stop thinking. data sheet, rev. 1.21, nov. 2005 communications adm8515/x usb2.0 to 10/100 mbit/s ethernet lan controller adm8515/x
the information in this document is subject to change without notice. edition 2005-11-08 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: com_tmplt_a4 .fm / 1 / 2003-07-04 trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineo n technologies ag. 10bases?, easyport?, vdslite? are trademarks of infi neon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. usb2.0 to 10/100 mbit /s ethernet lan controller revision history: 2005-11-08, rev. 1.21 previous version: page/date subjects (major ch anges since last revision) 2003-04-10 rev. 1.0: first release of adm8515/x 2003-08-28 rev. 1.1: updated pin 5 and 6 definition 2004-05-07 rev. 1.2: updated to include infineon-admtek 2005-09-13 rev. 1.21: when changed to the new infineon format 2005-11-01 minor change. included green package information
data sheet 4 rev. 1.21, 2005-11-08 adm8515/x 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.1 data lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 pin description by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 physical layer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.4 led display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.5 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.6 regulator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.7 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.8 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.1 pie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 ep decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 mac controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 jabber and sqe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.4 auto polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.5 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.6 baseline wander compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 fifo controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 fifo controller in receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.2 fifo controller in transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 tx fifo and rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 10/100m ethernet phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 usb device endpoint operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6.1 endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6.2 endpoint 1 bulk in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6.3 endpoint 2 bulk out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6.4 endpoint 3 interrupt in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 usb command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1 get register (vendor specific) single/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2 set register (vendor specific) burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3 get status (device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4 get status (interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5 get status (ep1) bulk in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6 get status (ep2) bulk out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.7 get status (ep3) interrupt in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table of contents
data sheet 5 rev. 1.21, 2005-11-08 adm8515/x 5.8 get descriptor (device) total 18-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.9 get descriptor (configuration) total 39-b yte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.10 get descriptor (string) index 0, languageid code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.11 get descriptor (string) index 1, manufa cture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.12 get descriptor (string) index 2, product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.13 get descriptor (string) index 3, serial no. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.14 get configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.15 get interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.16 get descriptor (device qualifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.17 get descriptor (other speed co nfiguration) total 39-b yte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.18 clear feature (device) remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.19 set feature (device) remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.20 clear feature (ep 0, 1, 2, 3) halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.21 set feature (ep 0, 1 ,2, 3) halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.22 set feature (test mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.1 usb interface dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.2 eeprom interface dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.3 gpio interface dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.1 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.4.2 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4.3 mii interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.1 appendix 1 eeprom content & example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
data sheet 6 rev. 1.21, 2005-11-08 adm8515/x figure 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4 packet form when receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5 packet form when transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 7 transmit signal timing relationships at the mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 8 received signal timing relations at the mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 9 mdio sourced by sta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 10 mdio sourced by phy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11 p-lqfp-100-1 (plastic low profile quad flat package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 list of figures
data sheet 7 rev. 1.21, 2005-11-08 adm8515/x table 1 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5 dm and dp signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6 mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7 physical layer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8 led display mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10 regulator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13 usb received status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14 usb packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15 interrupt packet form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16 interrupt packet form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20 registers clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22 wakeup frame 0 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23 wakeup frame 1 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24 wakeup frame 2 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 25 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 26 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 29 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 31 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 32 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 33 1st out transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 34 2nd out transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 35 3rd out transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 36 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 37 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 39 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 40 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 41 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 42 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 43 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 44 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 45 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 46 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 47 data stage: wlength fiel d specifies the total byte count to return . . . . . . . . . . . . . . . . . . . . . . 71 table 48 *8/64 := usb 1.1/2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 49 *8/64 := usb 1.1/2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 50 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 51 configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 52 configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 53 interface 0 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 list of tables
data sheet 8 rev. 1.21, 2005-11-08 adm8515/x table 54 ep1 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 55 ep2 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 56 ep3 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 57 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 58 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 59 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 60 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 61 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 62 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 63 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 64 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 65 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 66 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 67 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 68 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 69 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 70 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 71 data stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 72 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 73 configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 74 configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 75 interface 0 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 76 ep1 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 77 ep2 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 78 ep3 descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 79 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 80 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 81 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 82 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 83 setup stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 84 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 85 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 86 usb interface dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 87 eeprom interface dc specif ication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 88 gpio interface dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 89 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 90 dimensions for 100 pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 91 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 list of tables
data sheet 9 rev. 1.21, 2005-11-08 adm8515/x product overview 1 product overview the adm8515/x, usb based chip set, provides de sktop, notebook and computer peripheral with greater connectivity and data-trans mission to ethernet and home network. the adm8515x is the environmentally friendly ?green? package version. the adm8515/x device combines usb2.0 transceiver with utmi interface, an ep decoder used for usb interface through parallel interface engine (pie), fifo controller with 24k sram, 64 byte and 2k byte buffers, 10/100 mbit/s ethernet physical layer (phy) and mii interface. it is capable of providing an easy, universal connectivi ty to computer peripherals with usb. the transfer rate of usb interface is 480 mbit/s belonging to a high spee d usb device. the adm8515/x supports all usb commands, 4 endpoints and suspend/resume function. the adm8515/x?s lan phy supports 100 base tx (100 mbit/s mode) and 10 base t (10 mbit/s mode) full-duplex operations. it uses the auto-negotiati on function to optimize the network traffic and the built-in 24k bytes sram for receiving buffer, especially for 100 mbit/s. through fi fo controller, data can communicate in fluently between buffers and external device. to obtain the better signal quality, the phy provides wave -shaper, filter and adaptive equalizer to reach. by using diagno stic mechanism (loop-back mode), the data correct ness will be increased. the lan phy supports external transmit/receive transfor mer turn ratio 1:1. the adm8515/x chip set can be programmed for mac analysis and provides mii interface for external phy, such as mii interface for homepna and homeplug. in system app lication, eeprom is essentia l in that it needs to load device id, vendor id automatically. so for adm8515/x, seri al interface is applied for eeprom communication including read/write function. furthermore, some led pins report system statuses. infineon- admtek provides an eeprom access program utility for pr ogramming vendor id, product id etc. adm8515/x is ideally suited for usb adapter and intelligen t networked peripheral design. it can also be used in wide area network (wan), such as xdsl, cable modem, router, and information appliance (ia) application etc. 1.1 package information 1.2 features main features: ? industrial standard ? ieee 802.3u 100 base-tx and ieee 802. 3 10bbase-t compliant ? supports ieee 802.3x flow control ? supports ieee 802.3u auto-negotiation for 10base-t and 100base-tx ? usb specification 2.0 compliant ? usb interface ? high speed usb device ? supports 1 usb configuration and 1 interface ? supports all usb standard commands ? supports two vendor specific commands ? supports usb suspend/resume detection logic ? supports 4 endpoints: 1 control endpoint with maximu m 64-byte packet, 1 bulk in endpoint with maximum 512-byte packet, 1 bulk out endpoint with maximu m 512-byte packet and 1 interrupt in endpoint with maximum 8-byte packet ? mac/phy table 1 package information product name product type package ordering number adm8515/x adm8515/x-ac-t-1 p-lqfp-100-1 q67801h 24a101
data sheet 10 rev. 1.21, 2005-11-08 adm8515/x product overview ? integrates the whole physical la yer functions of 100 base-tx and 10base-t by using phy address 1 ? can be programmed to isolate the internal phy, supports mii interface to external 10/100 phy ? supports configurable threshold for pause frame ? supports wakeup frame, link status change and magic packet wake-up ? supports full-duplex operation on both 100 mbit/s and 10mbit/s speed modes ? supports auto-negotiation (n-way) function of fu ll/half duplex operation for both 10/100 mbit/s ? provides transmit wave-shaper, re ceives filter, an d adapter equalizer ? provides mlt-3 transceiver with dc restor ation for base-line wander compensation ? supports mac and transceiver loop back diagnostic modes ? supports external transmit/receive transformer with turn ratio 1:1 ? eeprom interface ? provides serial interface to access 93c46 eeprom ? automatically load device id, vendor id from eeprom afte r power-on reset ? fifo ? supports internal 2k bytes sram for transmission ? supports internal 24k bytes syn chronous sram for receiving ? led interface ? provides 4 led display modes ? provides usb full speed/high speed display modes ? support power save function @ usb suspend mode ? mode 0: resume by remote wakeup or host when os goes into standby ? mode 1: resume by host when os goes into standby. ? power consumption < 2.5 ma @ mode 1 ? support software ? windows 98/me/2000/xp driver ? linux driver ? wince 3.0 & 4.0 drivers ? eeprom burn-in program ? mfg testing program ? miscellaneous ? supports 6 gpio pins ? provides 100-pin lqfp package ? 3.3 v power supply with 5 v/3.3 v i/o tolerance
data sheet 11 rev. 1.21, 2005-11-08 adm8515/x product overview 1.3 block diagram figure 1 block diagram 1.4 conventions 1.4.1 data lengths qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits
data sheet 12 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2 interface description 2.1 pin diagram pin diagram of adm8515/x. figure 2 pin diagram
data sheet 13 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2 pin description by function adm8515/x pins are categorized into one of the following groups: ? host interface ? mii interface ? physical layer interface ? led display mode ? eeprom interface ? regulator pins ? power pins ? miscellaneous table 2 abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 3 abbreviations for buffer type abbreviations description z high impedance pu1 pull up, 10 k ? pd1 pull down, 10 k ? pd2 pull down, 20 k ? ts tristate capability: the corr esponding pin has 3 operationa l states: low, high and high- impedance. od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to shar e as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provid ed by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pi n can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics
data sheet 14 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.1 host interface table 4 host interface pin or ball no. name pin type buffer type function 8 i_clk12 i input clock 12 mhz clock input from crystal or oscillator. 7 o_clk12 o output for crystal 95 rst# i external hardware reset input schmitt trigger, internal pull high. 94 poren_n i internal power on reset logic enable default is enable and internal pull-low. when external hardware reset is used, this pin should be connected to vcc via 4.7 k ? resistor. 32 vph i/o usb d + port for high speed 30 vmh i/o usb d - port for high speed 33 vpf i/o usb d + port for full speed 31 vmf i/o usb d - port for full speed 28 rref pull down with 510 ohm precise resistor ( 1%) 35 rpu pull up with a 1.5 k ohm resistor 42 line0 o usb line state they directly reflect the current state of the dp (line1) and dm (line0) signals, see table 5 43 line1 table 5 dm and dp signals dm dp description 000: se0 0 1 1: ?j? state 1 0 2: ?k? state 113: se1
data sheet 15 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.2 mii interface note: program adm8515/x as mac-only mode, set register 81 h [4:2] = 001 b and register 01 h bit 2 = 0 table 6 mii interface pin or ball no. name pin type buffer type function 53 col i collision detected this signal is asserted high asynchronously by the external physical unit upon detection of a collision on the medium. it will remain asserted as long as the collision condition persists. 52 crs i carrier sense this signal is asserted high asynchronously by the external physical unit upon detection of a non-idle medium. 72 mdc o management data clock clock signal with a maximum rate of 2.5 mhz used to transfer management data for the external pmd on the mdio pin. 73 mdio i/o management data i/o bi-directional signal used to transfer management information for the external pmd. requires a 1.5 k ? pull-up resistor if external phy is used. 64 rxclk i receive clock a continuous clock that is recovered from the incoming data. during 100 mbit/s operation, rxclk is 25 mhz. during 10 mbit/s, this is 2.5 mhz. 71 rxd3 i receive data this is a group of 4 data signals aligned on nibble boundary which are driven synchronous to the rxclk by the external physical unit. rxd[3] is the mo st significant bit and rxd[0] is the least significant bit. 69 rxd2 68 rxd1 67 rxd0 65 rxdv i receive data valid this indicates that the external physical unit is presenting recovered and decoded nibbles on the rxd[3:0] and that rxclk is synchronous to the recovered data 63 rxer i receive error this signal is asserted high synchronously by the external physical unit whenever it detects a media error and rxdv is asserted. if not used, it sh ould be grounded, e.g. isolate internal phy and use external phy. 62 txclk i transmit clock a continuous clock that gets its source by the physical layer. during 100 mbit/s oper ation, this clock is 25 mhz. during 10 mbit/s operation, this clock is 2.5 mhz.
data sheet 16 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.3 physical layer interface 54 txd3 o transmit data this is a group of 4 data signals which are driven synchronously to the txclk for transmission to the external physical unit. txd[3] is the most significant bit and txd[0] is the least significant bit. 55 txd2 58 txd1 59 txd0 60 txen o transmit enable this signal is synchronous to txclk and provides precise framing for data carried on txd[3:0]. it is asserted when tx[3:0] contains valid data to be transmitted. requires external pull-down resistor 4.7 k ? if external phy is used. 74 xlnksts i link status indication external phy reports link stat us information to system and level change trigger. connect to external phy?s link status report pin or pull-down to low if not used. table 7 physical layer interface pin or ball no. name pin type buffer type function 85 o_clk25 o crystal out 25 mhz 86 i_clk25 i crystal in 25 mhz 78 rxip i receives inputs the differential receives inputs of 100base-tx or 10base-t, these pins direct ly input from magnetic. 77 rxin 88 txop o transmits outputs the differential transmit s outputs of 100base-tx or 10base-t, these pins dire ctly output to magnetic. 89 txon 83 ribb i reference bias resistor to be tied to an external 10.0 k ? (1%) resistor which should be connected to the analog ground at the other end. 80 antest_a o phy test pins 81 antest_b table 6 mii interface (cont?d) pin or ball no. name pin type buffer type function
data sheet 17 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.4 led display mode the led interface is eeprom program mable, 2 eeprom control bits, addr ess ob [7:6] in eeprom are used to select the led display mode. notes 1. eeprom 0b[7:6] = 00 b led0: 100 mbit/s (on, drive '0') or 10 mbit/s (off, drive '1') led1: link (keeps on when link on) or activity (flash with 10 hz when adm8515/x is receiving or transmitting without collision) led2: full duplex (keeps on when in full duplex mode) or collis ion (flash with 20 hz when collision occurred in half duplex mode) 2. eeprom 0b[7:6] = 01 b led0: activity (flash with 10 hz when adm8515 /x is receiving or tr ansmitting without collision) led1: link 10 (keeps on when link on 10 mbit/s) led2: link 100 (keeps on when link on 100 mbit/s) 3. eeprom 0b[7:6] = 10 b led0: 100 mbit/s (on, drive '0') or 10 mbit/s (off, drive '1') led1: activity (flash with 10 hz when adm8515 /x is receiving or tr ansmitting without collision) led2: link (keeps on when link on) 4. eeprom 0b[7:6] = 11 b led0: link 10 (led on when link on 10mbit/s) and activi ty (flash with 10hz when adm8515/x is receiving or transmitting without collision)led1: li nk 100 (led on when link on 100mbit/s) and ac tivity (flash with 10hz when adm8515/x is receiving or transm itting without collision) led2: full duplex (keeps on when in full duplex mode) table 8 led display mode pin or ball no. name pin type buffer type function 1led0o function of led0 function of led0 is described below. 2led1o function of led1 function of led1 is described below. 3led2o function of led2 function of led2 is described below. 5led3o led display for usb full led display for usb full speed rate link, active high. 6led4o led display for usb high led display for usb high speed rate link, active high.
data sheet 18 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.5 eeprom interface 2.2.6 regulator pins note: adm8515/x is a dual power device , it needs both 3.3 v and 2.5 v power supply. inside the chip, there is an embedded 3.3 v to 2.5 v power regulator that can generate the needed 2.5 v power to supply the chip. the reference schematics design is shown in figure 3 table 9 eeprom interface pin or ball no. name pin type buffer type function 48 eecs o eeprom chip select this pin enables the eeprom during loading of the ethernet configuration data. 46 eedi o eeprom data in adm8515/x will use this pin to serially write opcodes, addresses and da ta into the serial eeprom. 45 eedo i eeprom data out adm8515/x will read t he contents of th e eeprom serially through this pin. 47 eesk o eeprom clock after reset, adm8515/x will auto -load the contents of the eeprom by using eesk, eedo, and eedi. this pin provides the clock for the eeprom device. table 10 regulator pins pin or ball no. name pin type buffer type function 100 vddah p chip regulator 3.3 v power supply for on chip regulator. 98 vsa p ground for regulator 99 vctrl i/o regulator control pin 97 vsense i 2.5 v voltage sense input
data sheet 19 rev. 1.21, 2005-11-08 adm8515/x interface de scription figure 3 reference design 2.2.7 power pins table 11 power pins pin or ball no. name pin type buffer type function 12, 41, 57 vdd25 p 2.5 v power supply for core 13, 40, 56 vss25 p ground for vdd25 4, 49, 61, 70, 96 vddio p 3.3 v power supply for i/o 22, 44, 51, 66, 93 vssio p ground for vddio 26 dvdd1 p 2.5 v digital power supply 39 dvdd2 36 dgnd1 p digital ground 38 dgnd2 27 avdd1 p 3.3 v analog power supply 34 avdd2 29 agnd1 p analog ground 37 agnd2 90 vaat p 3.3 v power supply for transmitter 87 gndt p ground for vaat 76 vaar p 3.3 v power supply for receiver 79 gndr p ground for vaar 84 vaaref p 3.3 v power supply for phy 82 gndref p ground for vaaref
data sheet 20 rev. 1.21, 2005-11-08 adm8515/x interface de scription 2.2.8 miscellaneous table 12 miscellaneous pin or ball no. name pin type buffer type function 19 gpio5 i/o general purpose input/output pins these pins are used as general purpose input/output pins. these pins are internal pull-low. 20 gpio4 21 gpio3 23 gpio2 24 gpio1 25 gpio0 92, 91 test 1 i test pins 9, 10, 11, 14, 15, 16, 17, 18 test2 i/o test pins
data sheet 21 rev. 1.21, 2005-11-08 adm8515/x function description 3 function description 3.1 usb interface usb is a straightforward solution when you want to us e a computer for communication with devices outside the computer. the interface is suitable for one-of-kind and small-scale designs as well as mass-produced, standard peripheral. the be nefits of usb are easy to use a nd easy to apply, fast and reliabl e data transfers, flexibility, cost, and power conservation. 3.1.1 pie pie (parallel interface engine) is to control usb communications an d check usb protocol, then transfer protocol to ep decoder. the pie and usb transceivers, which prov ide the hardware interface to the usb cable, together comprise the usb engine. 3.1.2 ep decoder the detail description is in section 4.5 usb command. 3.2 mac controller 3.2.1 mii the media independent interface (mii) is an 18 wire mac/ phy interface described in 802.3u. the purpose of the interface is to allow mac layer devi ces to attach to a variety of phys ical layer devices through a common interface. mii operates at 100 mbit/s or 10 mbit/s, dependant on the speed of the physical layer. with clocks running at either 25 mhz or 2.5 mhz, 4 bit data is clocked between the mac and phy, synchronous with enable and error signals. on receipt of valid data fr om the wire interface, rx_dv will go active si gnaling to the mac that the valid data will be presented on the rxd[3:0] pi ns at the speed of the rx_clk. on transmission of data from the mac, tx_en is presented to the phy indi cating the presence of valid data on txd[3:0]. txd[3:0] are sampled by the phy synchronous to tx_clk during the time that tx_en is valid. 3.2.2 adaptive equalizer the amplitude and phase distortion from a cable causes inter-symbol inte rference (isi) which makes clock and data recovery difficult. the adaptive equalizer is designe d to closely match the inverse transfer function of the twisted-pairs cable. the equa lizer has the ability to change its equalizer freq uency response acco rding to the cable length. the equalizer will tu ne itself automatically fo r any cable, compensating for the amplitude and phase distortion introduced by the cable. 3.2.3 jabber and sqe after the mac transmitter exceeds the jabber timer, the transm it and loop back function s will be disabled and col signal gets asserted. after tx _en goes low for more than 500 ms, the tp transmitte r will reactivate and col gets de-asserted. setting ja bber disable will disabl e the jabber function. when the sqe test is enabled, a col pulse is asse rted after each transmitted packet. sqe is enabled in 10base-t by default.
data sheet 22 rev. 1.21, 2005-11-08 adm8515/x function description 3.2.4 auto polarity certain cable plants have crossed wiring on the twiste d pairs; the reversal of txin and txip. under normal circumstances this would cause the receiv e circuitry to reject all data. when the auto polarity disable bit is cleared, the phy has the ability to detect the fact that either 8 normal link pulses (nlp) or a burst of flps are inverted and automatically reverse the receiver ?s polarity. the polarity state is stored in the reverse polarity bit. 3.2.5 auto-negotiation it provides a linked device with the ca pability to detect the abilit ies (modes of operations) supported by the device at the other en d of the link, determine common abilities, and configure for joint operation. auto-negotiation is performed out-of-band usin g a pulse code sequence th at is compatible with t he 10base-t link integrity test sequence. 3.2.6 baseline wander compensation the 100base-tx data stream is not always dc balanced . the transformer blocks t he dc components of the incoming signal, thus the dc offset of the differential rece ive inputs can drift. the shifting of the signal level, coupled with non-zero rise and fall times of the serial st ream can cause pulse-width di stortion. this creates jitter and possible increase in the bit error rates. therefore, a dc restoration circuit is needed to compensate for the attenuation of the dc component. un like the traditional impl ementation, the circuit does not need the feedback information from the slicer or the cl ock recovery circuit. the design simplif ies the circuit design. in 10base-t, the baseline wander correction circuit is not required. 3.3 fifo controller 3.3.1 fifo controller in receive path ? store received ethernet packets to sram (internal 24 kbyte) and total 16 packets can be stored to sram. if more than 16 packets are received or total packet size is more than 24 kbytes, the subsequent coming ethernet packet will be discarded. ? fifo controller will load data from sram to internal rx fifo then inform ep decoder that 512-byte data or a packet is ready in rx fifo . before fifo controller in forms about this, any usb access to bulk in endpoint will return nak. this is to maintain the data transfer on usb bus via bulk in transfer is continuous, thus a 512-byte internal rx fifo is needed. ? if an ethernet packet is being received and loading into sram while fifo cont roller is moving data from sram to internal rx fifo, writing the ethern et packet to sram will get the higher priority. 3.3.2 fifo controller in transmit path ? store each individual usb packet to internal tx fifo. when ep decoder informs end of packet, a complete ethernet packet is stored in tx fifo. fifo controller then inform s mac to transmit this packet. ? total 4 ethernet packets can be stored in tx fifo. if all 4 ethernet packets are stored in tx fifo or total packet size is more than 2 kbytes, fifo controller will inform ep decoder that tx fifo is full and ep decoder will return nak if accessing to bulk out endpoint is invoked. thus addi tional usb packet won?t be written into tx fifo until tx fifo has free space. 3.4 tx fifo and rx fifo rx fifo is a one-port 512 byte fifo an d tx fifo is a two-port 2 kbyte fifo
data sheet 23 rev. 1.21, 2005-11-08 adm8515/x function description 3.5 10/100m ethernet phy the ethernet phy is compli ant to ieee 802.3u 100base-tx and ieee 802.3 10base-t. it pr ovides the whole physical layer functions for bo th 10m and 100m ethernet speed. 3.6 usb device endpoint operation 3.6.1 endpoint 0 endpoint 0 is in charge of response to standard usb co mmands and vendor specific commands. internal register settings are also via this endpoint 0. the resp onse to each command is described in ?usb commands?. 3.6.2 endpoint 1 bulk in endpoint 1 is in charge of sending th e received ethernet packet to usb host. an ethernet packet will be split to multiple 512 bytes usb packets on usb. the end of the et hernet packet is indicated by less then 512 byte or 0 length data transfer in this pipe. the ethernet received status is optionally reported at the end of the packet. while accessing to this endpoint, if rxfifo is either full or any packet is inside, the data in rxfifo is returned in usb data stage. if ack is received from usb host, data in rxfifo is flushed. if no response or nak is received from usb host, the content in rxfifo will be re-transmitted. if rxfifo isn?t ready for transmission, nak is returned to usb host. figure 4 packet form when receive the received status is reported as follows: table 13 usb received status offset bit field description offset0 7-0 rx_bytecnt_lo the received byte count[7:0]. offset1 3-0 rx_bytecnt_hi the received byte count[11:8]. 7-4 reserved offset2 0 multicast_frame indicat es received multicast frame. 1 long_pkt indicates received packet length > 1518 bytes. 2 runt_pkt indicates received packet length < 64 bytes. 3 crc_err indicates crc check error. 4 dribble_bit indicates packet length is not integer multiple of 8- bit. 7-5 reserved offset3 7-0 reserved
data sheet 24 rev. 1.21, 2005-11-08 adm8515/x function description 3.6.3 endpoint 2 bulk out endpoint 2 is in charge of sending the usb packet to ethernet. an ethernet packet is concatenated by multiple 512 bytes usb packets on usb. the first two bytes in ev ery first concatenated usb pa cket indicate the length of the ethernet packet. the end of the ethernet packet is indica ted by less then 512-byte or 0 length data transfer in this pipe. the ethernet transmit status is reported in transmit status register. when access to this endpoint, data in usb data stage ar e transferred to txfifo, if txfifo is free and ack is returned. if txfifo isn? t free, nak is returned. figure 5 packet form when transmit 3.6.4 endpoint 3 interrupt in endpoint 3 is in charge of returning the current et hernet transfer status every po lling interval. when access to this endpoint, 8 bytes data is returned to usb host. the 8-by te packet contains the following in the tables below: table 14 usb packet format field 1st byte in 1st usb packet 2nd byte in 1st usb packet the following packets content len[7:0]: low byte ethernet packet length {reserved[4:0], len[10 :8]} ethernet packet table 15 interrupt packet form offset0 offset1 offset2 offset3 offset4 tx_status(reg2b h ) tx_status(reg2c h ) rx_status(reg2d h ) rx_lostpkt(reg2e h ) rx_lostpkt(reg2f h ) table 16 interrupt packet form offset5 offset6(1b) offset7(1b) wakeup_status(reg7a h ) packet number in rx fifo (reg82 h ) 7?b00, length error
data sheet 25 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers 4 registers description 4.1 system registers table 17 registers address space module base address end address note 0000 0000 h 0000 0082 h table 18 registers overview register short name register long name offset address page number ec0 ethernet control 0 00 h 28 ec1 ethernet control 1 01 h 29 ec2 ethernet control 2 02 h 30 res0 reserved 0 03 h 31 res1 reserved 1 04 h 31 res2 reserved 2 05 h 31 res3 reserved 3 06 h 31 res4 reserved 4 07 h 31 ma0 multicast address 0 08 h 32 ma1 multicast address 1 09 h 32 ma2 multicast address 2 0a h 33 ma3 multicast address 3 0b h 33 ma4 multicast address 4 0c h 34 ma5 multicast address 5 0d h 34 ma6 multicast address 6 0e h 35 ma7 multicast address 7 0f h 35 eid0 ethernet id 0 10 h 36 eid1 ethernet id 1 11 h 36 eid2 ethernet id 2 12 h 37 eid3 ethernet id 3 13 h 37 eid4 ethernet id 4 14 h 38 eid5 ethernet id 5 15 h 38 res5 reserved 5 16 h 31 res6 reserved 6 17 h 31 pt pause timer 18 h 39 res7 reserved 7 19 h 31 rpnbfc receive packet number based flow control 1a h 39 orfbfc occupied receive fifo based flow control 1b h 40 ep1c ep1 control 1c h 40 res8 reserved 8 1d h 31
adm8515/x registers descriptionsystem registers data sheet 26 rev. 1.21, 2005-11-08 bist bist 1e h 40 res9 reserved 9 1f h 31 eepromo eeprom offset 20 h 41 eepromdl eeprom data low 21 h 41 eepromdh eeprom data high 22 h 42 eepromac eeprom access control 23 h 43 res10 reserved 10 24 h 31 phya phy address 25 h 43 phydl phy data low 26 h 44 phydh phy data high 27 h 44 phyac phy access control 28 h 45 res11 reserved 11 29 h 31 usbbs usb bus status 2a h 45 ts1 transmit status 1 2b h 45 ts2 transmit status 2 2c h 47 rs receive status 2d h 47 rlpch receive lost packet count high 2e h 48 rlpcl receive lost packet count low 2f h 48 wuf0m_0 wakeup frame 0 mask 30 h 48 wuf0m_1 wakeup frame 0 mask 1 31 h 49 ... ... ... h 49 wuf0m_xx wakeup frame 0 mask xx 3f h 49 wuf0o_0 wakeup frame 0 offset 40 h 49 wuf0crcl wakeup frame 0 crc low 41 h 50 wuf0crch wakeup frame 0 crc high 42 h 50 res12 reserved 12 43 h 31 res13 reserved 13 44 h 31 res14 reserved 14 45 h 31 res15 reserved 15 46 h 31 res16 reserved 16 47 h 31 wuf1m_0 wakeup frame 1 mask 48 h 51 wuf1m_1 wakeup frame 1 mask 1 49 h 51 ... ... ... h 51 wuf1m_xx wakeup frame 1 mask xx 57 h 51 wuf1o wakeup frame 1 offset 58 h 51 wuf1crcl wakeup frame 1 crc low 59 h 52 wuf1crch wakeup frame 1 crc high 5a h 52 res17 reserved 17 5b h 31 res18 reserved 18 5c h 31 res19 reserved 19 5d h 31 res 20 reserved 20 5e h 31 table 18 registers overview (cont?d) register short name register long name offset address page number
data sheet 27 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers the register is addressed wordwise. res 21 reserved 21 5f h 31 wuf2m wakeup frame 2 mask 60 h 53 wuf2m_1 wakeup frame 2 mask 1 61 h 53 ... ... ... h 53 wuf2m_xx wakeup frame 2 mask xx 6f h 53 wuf2o wakeup frame 2 offset 70 h 53 wuf2crcl wakeup frame 2 crc low 71 h 54 wuf2crch wakeup frame 2 crc high 72 h 54 res 22 reserved 22 73 h 31 res 23 reserved 23 74 h 31 res 24 reserved 24 75 h 31 res 25 reserved 25 76 h 31 res 26 reserved 26 77 h 32 wuc wakeup control 78 h 55 res 27 reserved 27 79 h 32 wus wakeup status 7a h 56 iphyc internal phy control 7b h 56 gpio54c gpio[5:4] control 7c h 57 res 28 reserved 28 7d h 32 gpio10c gpio[1:0] control 7e h 58 gpio32c gpio[3:2] control 7f h 59 test test 80 h 60 tm test mode 81 h 60 rpn receive packet number 82 h 61 res 29 reserved 29 83 h 32 ... ... ... h 32 res xx reserved xx ff h 32 table 19 register access types mode symbol description hw description sw read/write rw register is used as input for t he hw register is readable and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register table 18 registers overview (cont?d) register short name register long name offset address page number
adm8515/x registers descriptionsystem registers data sheet 28 rev. 1.21, 2005-11-08 4.1.1 registers ethernet control 0 latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interrupt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is readable and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be clea red due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is readable and writable by sw. table 20 registers clock domains clock short name description ec0 offset reset value ethernet control 0 00 h 09 h table 19 register access types (cont?d) mode symbol description hw description sw uz 7;( uz 5;( uz 5;)&( uz :2( uz 5;6$ uz 6%2 uz 5;0$ uz 5;&6
data sheet 29 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers ethernet control 1 field bits type description txe 7 rw ethernet transmission enable 1 b tx_en , enable rxe 6 rw ethernet receive enable 1 b rx_en , enable rxfce 5 rw receive pause frame enable 1 b rx_flowctl_en , enable woe 4 rw wake-on-lan mode enable 1 b wakeon_en , enable rxsa 3 rw status append at the end of received packet 1 b rxstatus_append , enable sbo 2 rw stop back off 0 b cnot , back-off counter isn? t affected by carrier 1 b cst , back-off counter stop when carrier is active and resume when carrier drop rxma 1 rw receive all multicast packets 1 b rall , receives all multicast packets rxcs 0 rw include crc in receive packet 1 b icrc , includes crc in receive packet ec1 offset reset value ethernet control 1 01 h 00 h field bits type description fd 5 rw full dublex 0 b hdm , half-duplex mode 1 b fdm , full-duplex mode 10m 4 rw 10mode 0 b 10base , 10base-t mode 1 b 100base , 100base-t mode rm 3 rw reset mac after write 1, hw will clear this bit after mac reset. 5hv uz )' uz 0 uz 50 5hv
adm8515/x registers descriptionsystem registers data sheet 30 rev. 1.21, 2005-11-08 ethernet control 2 ec2 offset reset value ethernet control 2 02 h 40 h field bits type description mepl 7 rw max ethernet packet length 0 b 1528b , 1528 bytes 1 b 1638b , 1638 bytes, default is 0 rpnc 6 rw receive packet number control this bit controls the clea r operation of register 82 h (receive packet number register) 0 b nrc , no read clear 1 b rc , read clear leeprs 5 rw load eeprom start when this bit is written with 1, hw will start to load eeprom. eeprw 4 rw eeprom write enable/disable 0 b wedc , eeprom write enabl e/disable command 1 b wc , eeprom write command lb 3 rw loop back enable mac loop back mode. prom 2 rw promiscuous 0 b rpp , receives packets which pass the address filter 1 b rap , receives any packets rxbp 1 rw receive bad packets 0 b fabp , filter all bad packet 1 b rbpp , receives bad packets which pass the address filter ep3rc 0 rw ep3 read cleared 0 b aep3 , access ep3, no effect to those registers. 1 b oep3 , once ep3 is accessed, thos e registers (2b-2f, 7a) will be cleared. uz 0(3/ uz 531& uz /((356 uz ((35: uz /% uz 3520 uz 5;%3 uz (35&
data sheet 31 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers reserved 0 similar registers res0 offset reset value reserved 0 03 h 00 h field bits type description res 7:0 ro reserved table 21 reserved registers register short name register long name offset address page number res1 reserved 1 04 h res2 reserved 2 05 h res3 reserved 3 06 h res4 reserved 4 07 h res5 reserved 5 16 h res6 reserved 6 17 h res7 reserved 7 19 h res8 reserved 8 1d h res9 reserved 9 1f h res10 reserved 10 24 h res11 reserved 11 29 h res12 reserved 12 43 h res13 reserved 13 44 h res14 reserved 14 45 h res15 reserved 15 46 h res16 reserved 16 47 h res17 reserved 17 5b h res18 reserved 18 5c h res19 reserved 19 5d h res 20 reserved 20 5e h res 21 reserved 21 5f h res 22 reserved 22 73 h res 23 reserved 23 74 h res 24 reserved 24 75 h res 25 reserved 25 76 h ur 5hv
adm8515/x registers descriptionsystem registers data sheet 32 rev. 1.21, 2005-11-08 multicast address 0 multicast address 1 res 26 reserved 26 77 h res 27 reserved 27 79 h res 28 reserved 28 7d h res 29 reserved 29 83 h ... ... ... h res xx reserved xx ff h ma0 offset reset value multicast address 0 08 h 00 h field bits type description mab0 7:0 rw multicast 0 multicast address byte [7:0] ma1 offset reset value multicast address 1 09 h 00 h field bits type description mab1 7:0 rw multicast 1 multicast address byte [15:8] table 21 reserved registers register short name register long name offset address page number uz 0$% uz 0$%
data sheet 33 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers multicast address 2 multicast address 3 ma2 offset reset value multicast address 2 0a h 00 h field bits type description mab2 7:0 rw multicast 2 multicast address byte [23:16] ma3 offset reset value multicast address 3 0b h 00 h field bits type description mab3 7:0 rw multicast 3 multicast address byte [31:24] uz 0$% uz 0$%
adm8515/x registers descriptionsystem registers data sheet 34 rev. 1.21, 2005-11-08 multicast address 4 multicast address 5 ma4 offset reset value multicast address 4 0c h 00 h field bits type description mab4 7:0 rw multicast 4 multicast address byte [39:32] ma5 offset reset value multicast address 5 0d h 00 h field bits type description mab5 7:0 rw multicast 5 multicast address byte [47:40] uz 0$% uz 0$%
data sheet 35 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers multicast address 6 multicast address 7 ma6 offset reset value multicast address 6 0e h 00 h field bits type description mab6 7:0 rw multicast 6 multicast address byte [55:48] ma7 offset reset value multicast address 7 0f h 00 h field bits type description mab7 7:0 rw multicast 7 multicast address byte [63:56] uz 0$% uz 0$%
adm8515/x registers descriptionsystem registers data sheet 36 rev. 1.21, 2005-11-08 ethernet id 0 ethernet id 1 eid0 offset re set value ethernet id 0 10 h 00 h field bits type description eid0 7:0 rw ethernet id 0 the 1st byte of ethernet id is au tomatically loaded from eeprom after hw reset. eid1 offset re set value ethernet id 1 11 h 00 h field bits type description eid1 7:0 rw ethernet id 1 the 2nd byte of ethernet id. uz (,' uz (,'
data sheet 37 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers ethernet id 2 ethernet id 3 eid2 offset re set value ethernet id 2 12 h 00 h field bits type description eid2 7:0 rw ethernet id 2 the 3rd byte of ethernet id. eid3 offset re set value ethernet id 3 13 h 00 h field bits type description eid3 7:0 rw ethernet id 3 the 4th byte of ethernet id. uz (,' uz (,'
adm8515/x registers descriptionsystem registers data sheet 38 rev. 1.21, 2005-11-08 ethernet id 4 ethernet id 5 eid4 offset re set value ethernet id 4 14 h 00 h field bits type description eid4 7:0 rw ethernet id 4 the 5th byte of ethernet id. eid5 offset re set value ethernet id 5 15 h 00 h field bits type description eid5 7:0 rw ethernet id 5 the 6th byte of ethernet id. uz (,' uz (,'
data sheet 39 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers pause timer receive packet number based flow control pt offset reset value pause timer 18 h 00 h field bits type description pt 7:0 rw pause timer the [11:4] of pause time in the pause frame. rpnbfc offset reset value receive packet number based flow control 1a h 00 h field bits type description pn 6:1 rw packet number this field specifies the threshold for transmitting the pause frame. as the received packet number is more than or equal to this field, the pause frame is sent automatically by hw. fcp 0 rw flow control packet 1 b rpn , enable pause frame transmission bases on receive packet number uz 37 5hv uz 31 uz )&3
adm8515/x registers descriptionsystem registers data sheet 40 rev. 1.21, 2005-11-08 occupied receive fifo based flow control ep1 control bist orfbfc offset reset value occupied receive fifo based flow control 1b h 00 h field bits type description rxs 6:1 rw rx size this field specifies the kbyte threshold for transmitting the pause frame. as the received fifo is occupied than or equal to this field, the pause frame is sent automatically by hw. if this field = 2, as receive fifo is occupied more than or equal to 2 kbyte, the pause frame is transmitted. fcrxs 0 rw flow control rx size 1 b rfs , enable pause frame transmission bases on occupied receive fifo size ep1c offset reset value ep1 control 1c h 04 h field bits type description ep1s0e 7 rw ep1 send enable 0 b dep1 , disable ep1 send 1-byte 00 function 1 b eep1 , enable ep1 send 1-byte 00 when more than frame_ interval?s nak is received itma 6:5 rw internal test mode a this value is used for internal test mode. itmb 4:0 rw internal test mode b this value is used for internal test mode. 5hv uz 5;6 uz )&5;6 uz (36( uz ,70$ uz ,70%
data sheet 41 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers eeprom offset eeprom data low bist offset re set value bist 1e h 05 h field bits type description br 2 r bist result this bit indicates the bist result and is valid when ?bist_te st_done? is ?1?. this bit also reflects the value of ?p ass_or_fail? signal in bist module. 0 b fa , fail 1 b pa , pass btd 1 r bist test done this bit indicates the completion of bist. the bist completes if this bit is ?1?. this bit also reflects the value of ?test_done? signal in bist module. ben 0 rw bist enable this bit enable the bist function and also drives the ? reset? signal in bist module. 0 b ebi , enable bist function 1 b dbi , disable bist function eepromo offset reset value eeprom offset 20 h 00 h field bits type description romo 5:0 rw rom offset sw sets this register when access to eeprom. eepromdl offset reset value eeprom data low 21 h 00 h 5hv u %5 u %7' uz %(1 5hv uz 5202
adm8515/x registers descriptionsystem registers data sheet 42 rev. 1.21, 2005-11-08 eeprom data high field bits type description romdl 7:0 rw rom data low eeprom write: the data set in this register will be written to eeprom eeprom read: the data red from eeprom will be stored in this register eepromdh offset reset value eeprom data high 22 h 00 h field bits type description romdh 7:0 rw rom data high eeprom write: the data set in this register will be written to eeprom eeprom read: the data red from eeprom will be stored in this register uz 520'/ uz 520'+
data sheet 43 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers eeprom access control phy address eepromac offset reset value eeprom access control 23 h 00 h field bits type description do 2 rw done set by hw to indicate successful completion of eepr om access. clear by sw when initiate a new access to eeprom rde 1 rw read access to eeprom rd_eeprom set by sw to initiate a read access to eeprom. sw sets th is bit after it well setting the rom_offset. wre 0 rw write access to eeprom wr_eeprom set by sw to initiate a write access to eeprom. sw set this bit after it well setting the rom_offset, romdata_lo and romdata_hi. phya offset re set value phy address 25 h 00 h field bits type description phya 4:0 rw mii phy address 5hv uz '2 uz 5'( uz :5( 5hv uz 3+<$
adm8515/x registers descriptionsystem registers data sheet 44 rev. 1.21, 2005-11-08 phy data low phy data high phydl offset reset value phy data low 26 h 00 h field bits type description phydl 7:0 rw phy data low sw set this register when write to ph y register. hw set this register when read data from phy register. phydh offset reset value phy data high 27 h 00 h field bits type description phydh 7:0 rw phy data high sw set this register when write to ph y register. hw set this register when read data from phy register. uz 3+<'/ uz 3+<'+
data sheet 45 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers phy access control usb bus status transmit status 1 phyac offset reset value phy access control 28 h 00 h field bits type description do 7 rw done set by hw to indicate successful completion of phy access. clear by sw when initiate a new access to phy. rdphy 6 rw read access to phy register set by sw to initiate a read access to phy register. sw set this bit after it well setting the phy_addr and phyreg_addr. wrphy 5 rw write access to phy register set by sw to initiate a write access to phy register. sw set this bit after it well setting the phy_addr, phyreg_addr and phyreg_data. phyra 4:0 rw phy register address usbbs offset reset value usb bus status 2a h 00 h field bits type description usbr 1 rw usb bus in resume state it is cleared by reading this register. 1 b rs , means usb bus in resume state usbs 0 rw usb bus in suspend state it is cleared by reading this register. 1 b ss , means usb bus in suspend state uz '2 uz 5'3+< uz :53+< uz 3+<5$ 5hv uz 86%5 uz 86%6
adm8515/x registers descriptionsystem registers data sheet 46 rev. 1.21, 2005-11-08 ts1 offset reset value transmit status 1 2b h 00 h field bits type description txue 7 r tx underrun error it is cleared by reading this register or after ep3 is accessed 1 b txue , means tx underrun error ec 6 r excessive collision it is cleared by reading this register or after ep3 is accessed 1 b ec , means excessive collision lc 5 r late collision error it is cleared by reading this register or after ep3 is accessed 1 b ce , means late collision error nc 4 r no carrier it is cleared by reading this register or after ep3 is accessed 1 b nc , means no carrier cl 3 r carrier loss it is cleared by reading this register or after ep3 is accessed 1 b cl , means carrier loss jto 2 r jabber time out it is cleared by reading this register or after ep3 is accessed 1 b jto , means jabber time out u 7;8( u (& u /& u 1& u &/ u -72 5hv
data sheet 47 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers transmit status 2 receive status ts2 offset reset value transmit status 2 2c h 00 h field bits type description txff 7 r tx fifo full it is cleared by reading this register or after ep3 is accessed 1 b ff , means tx fifo full txfe 6 r tx fifo empty it is cleared by reading this register or after ep3 is accessed 1 b fe , means tx fifo empty txpc 3:0 r tx packet count it is cleared by reading this register or after ep3 is accessed. 1 b tpc , means ethernet transmit pack et count every interrupt ep polling. if more than 15 packets have been transmitted this value will keep as 15. rs offset reset value receive status 2d h 00 h field bits type description rxp 1 r rx pause it is cleared by reading this register or after ep3 is accessed 1 b pf , means a pause frame is received rxo 0 r rx overflow it is cleared by reading this register or after ep3 is accessed 1 b ro , means received sram overflow u 7;)) u 7;)( 5hv u 7;3& 5hv u 5;3 u 5;2
adm8515/x registers descriptionsystem registers data sheet 48 rev. 1.21, 2005-11-08 receive lost packet count high receive lost packet count low wakeup frame 0 mask rlpch offset reset value receive lost packet count high 2e h 00 h field bits type description rpl 7 r received packet lost it is cleared by reading this register or after ep3 is accessed. 1 b rpl , means received packet lost rxlpc 6:0 r rx lost packet counts the [14:8] of lost packet counts due to receive fifo overflow. it is cleared by reading this register or after ep3 is accessed. rlpcl offset reset value receive lost packet count low 2f h 00 h field bits type description rxlpc 7:0 r rx lost packet counts the [7:0] of lost packet counts due to receive fifo overflow. it is cleared by reading this register or after ep3 is accessed wuf0m_0 offset reset value wakeup frame 0 mask 30 h 00 h u 53/ u 5;/3& u 5;/3&
data sheet 49 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers similar registers wakeup frame 0 offset field bits type description f0m 7:0 rw the 128 mask bits for frame 0 table 22 wakeup frame 0 mask registers register short name register long name offset address page number wuf0m_1 wakeup frame 0 mask 1 31 h ... ... ... h wuf0m_xx wakeup frame 0 mask xx 3f h wuf0o_0 offset reset value wakeup frame 0 offset 40 h 00 h field bits type description f0o 7:0 rw offset for wakeup frame 0 uz )0 uz )2
adm8515/x registers descriptionsystem registers data sheet 50 rev. 1.21, 2005-11-08 wakeup frame 0 crc low wakeup frame 0 crc high wuf0crcl offset reset value wakeup frame 0 crc low 41 h 00 h field bits type description f0crcl 7:0 rw the low byte of crc16 match for frame 0 wuf0crch offset reset value wakeup frame 0 crc high 42 h 00 h field bits type description f0crch 7:0 rw the high byte of crc16 match for frame 0 uz )&5&/ uz )&5&+
data sheet 51 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers wakeup frame 1 mask similar registers wakeup frame 1 offset wuf1m_0 offset reset value wakeup frame 1 mask 48 h 00 h field bits type description f1m 7:0 rw the 128 mask bits for frame 1 table 23 wakeup frame 1 mask registers register short name register long name offset address page number wuf1m_1 wakeup frame 1 mask 1 49 h ... ... ... h wuf1m_xx wakeup frame 1 mask xx 57 h wuf1o offset reset value wakeup frame 1 offset 58 h 00 h field bits type description f1o 7:0 rw offset for wakeup frame 1 uz )0 uz )2
adm8515/x registers descriptionsystem registers data sheet 52 rev. 1.21, 2005-11-08 wakeup frame 1 crc low wakeup frame 1 crc high wuf1crcl offset reset value wakeup frame 1 crc low 59 h 00 h field bits type description 7:0 rw the low byte of crc16 match for frame 1 wuf1crch offset reset value wakeup frame 1 crc high 5a h 00 h field bits type description f1crch 7:0 rw the high byte of crc16 match for frame 1 uz uz )&5&+
data sheet 53 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers wakeup frame 2 mask similar registers wakeup frame 2 offset wuf2m offset reset value wakeup frame 2 mask 60 h 00 h field bits type description f2m 7:0 rw the 128 mask bits for frame 2 table 24 wakeup frame 2 mask registers register short name register long name offset address page number wuf2m_1 wakeup frame 2 mask 1 61 h ... ... ... h wuf2m_xx wakeup frame 2 mask xx 6f h wuf2o offset reset value wakeup frame 2 offset 70 h 00 h field bits type description f2o 7:0 rw offset for wakeup frame 2 uz )0 uz )2
adm8515/x registers descriptionsystem registers data sheet 54 rev. 1.21, 2005-11-08 wakeup frame 2 crc low wakeup frame 2 crc high wuf2crcl offset reset value wakeup frame 2 crc low 71 h 00 h field bits type description f2crcl 7:0 rw the low byte of crc16 match for frame 2 wuf2crch offset reset value wakeup frame 2 crc high 72 h 00 h field bits type description f2crch 7:0 rw the high byte of crc16 match for frame 2 uz )&5&/ uz )&5&+
data sheet 55 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers wakeup control wuc offset reset value wakeup control 78 h 04 h field bits type description emp 7 rw enable magic packet 1 b emp , enables magic packet wakeup function els 6 rw enable link status 1 b els , enables link status wakeup function ewf0 5 rw enable wakeup frame 0 1 b ewf0 , enables wakeup frame0 wakeup function wuf1 4 rw enable wakeup frame 1 1 b ewf1 , enables wakeup frame1 wakeup function wuf2 3 rw enable wakeup frame 2 1 b ewf2 , enables wakeup frame2 wakeup function crc16 2 rw crc-16 initial type 0 b crc16 , crc-16 initial contents = 0000 h 1 b crc16 , crc-16 initial contents = ffff h uz (03 uz (/6 uz (:) uz :8) uz :8) uz &5& 5hv
adm8515/x registers descriptionsystem registers data sheet 56 rev. 1.21, 2005-11-08 wakeup status internal phy control wus offset reset value wakeup status 7a h 00 h field bits type description rxmp 7 r receives a magic packet it is cleared by reading this register. 1 b rmp , means adm8515/x receives a magic packet lw 6 r receives a link status change it is cleared by reading this register. 1 b rls , means adm8515/x receives a link status change rxwf 5 r receives a wakeup frame it is cleared by reading this register. 1 b rwf , means adm8515/x receives a wakeup frame ls 0 r indicate the current link status 0 b loff , link off 1 b lon , link on iphyc offset reset value internal phy control 7b h 00 h field bits type description ephy 1 rw enable phy 0 b din , disables internal 10/100 phy 1 b ein , enables internal 10/100 phy phyr 0 rw internal phy reset the internal phy is reset when this bit is written with 1 and stops reset when this bit is written with 0. 1 b riphy , resets internal phy u 5;03 u /: u 5;:) 5hv u /6 5hv uz (3+< uz 3+<5
data sheet 57 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers gpio[5:4] control gpio54c offset reset value gpio[5:4] control 7c h 00 h field bits type description g5oe 5 rw gpio5 output enable 0 b in , gpio5 is used for input 1 b out , gpio5 is used for output g5ov 4 rw gpio5 output value when gpio5 is used for output, this value is driven to gpio5 pin. g5iv 3 r gpio5 input value when gpio5 is used for input, this field reflects the status of gpio5. default is pulled-down. g4oe 2 rw gpio4 output enable 0 b in , gpio4 is used for input 1 b out , gpio4 is used for output g4ov 1 rw gpio4 output value when gpio4 is used for output, this value is driven to gpio4 pin. g4iv 0 r gpio4 input value when gpio4 is used for input, this field reflects the status of gpio4. default is pulled-down. 5hv uz *2( uz *29 u *,9 uz *2( uz *29 u *,9
adm8515/x registers descriptionsystem registers data sheet 58 rev. 1.21, 2005-11-08 gpio[1:0] control gpio10c offset reset value gpio[1:0] control 7e h 00 h field bits type description g1oe 5 rw gpio1 output enable 0 b in , gpio1 is used for input 1 b out , gpio1 is used for output g1ov 4 rw gpio1 output value when gpio1 is used for output, this value is driven to gpio1 pin. g1iv 3 r gpio1 input value when gpio1 is used for input, this field reflects the status of gpio1. g1oe 2 rw gpio0 output enable 0 b in , gpio0 is used for input 1 b out , gpio0 is used for output g0ov 1 rw gpio0 output value when gpio0 is used for output, this value is driven to gpio0 pin. g0iv 0 r gpio0 input value when gpio0 is used for input, this field reflects the status of gpio0. 5hv uz *2( uz *29 u *,9 uz *2( uz *29 u *,9
data sheet 59 rev. 1.21, 2005-11-08 adm8515/x registers descriptionsystem registers gpio[3:2] control gpio32c offset reset value gpio[3:2] control 7f h 00 h field bits type description g3oe 5 rw gpio3 output enable 0 b in , gpio3 is used for input 1 b out , gpio3 is used for output g3ov 4 rw gpio3 output value when gpio3 is used for output, this value is driven to gpio3 pin. g3iv 3 r gpio3 input value when gpio3 is used for input, this field reflects the status of gpio3. g2oe 2 rw gpio2 output enable 0 b in , gpio2 is used for input 1 b out , gpio2 is used for output g2ov 1 rw gpio2 output value when gpio2 is used for output, this value is driven to gpio2 pin. g2iv 0 r gpio2 input value when gpio2 is used for input, this field reflects the status of gpio2. 5hv uz *2( uz *29 u *,9 uz *2( uz *29 u *,9
adm8515/x registers descriptionsystem registers data sheet 60 rev. 1.21, 2005-11-08 test test mode test offset reset value test 80 h 00 h field bits type description gs 5:0 rw internal probing signal group selection group_sel tm offset reset value test mode 81 h 00 h field bits type description txpc 7 rw tx packet control 0 b tli , transmits length in the fi rst 2 bytes could be ignored 1 b tlr , transmits length in the first 2 bytes is used as real data length pms 6 r power mode selection this bit is loaded from eeprom 0 b bp , bus power 1 b sp , self power mtm 4:2 rw mii test mode this value could be updated from eeprom offset 0a[4:2]. 000 b ts , tri-state mii pins 001 b em , enables mac?s mii signals to external mii pins 010 b ephy , enables phy?s mii signal s to external mii pins 011 b mm , monitor mode mii 5hv uz *6 uz 7;3& u 306 5hv uz 070 5hv
data sheet 61 rev. 1.21, 2005-11-08 adm8515/x registers descriptionphy registers receive packet number 4.2 phy registers the register is addressed wordwise. register access types 4.2.1 registers rpn offset reset value receive packet number 82 h 00 h field bits type description pn 7:0 r packet number received packet number from last acce ss this register. this register is controlled by reg 02[6] to decide read clear or not. table 25 registers address space module base address end address note phy registers 0000 0000 h 0000 0006 h table 26 registers overview register short name register long name offset address page number ctl control 0 h 62 sta status 01 h 63 phyi1 phy identifier 1 2 h 65 phyi2 phy identifier 2 3 h 65 ana auto-negotiation advertisement 4 h 66 anlpa auto-negotiation link partner ability 5 h 67 ane auto-negotiation expansion 6 h 67 u 31
adm8515/x registers descriptionphy registers data sheet 62 rev. 1.21, 2005-11-08 control note: sc self clearing reset reset this port only. th is will cause the following: 1. restart the auto-negotiation process. 2. reset the registers to their default values. note that this does not affect registers 20, 22, 30 or 31. these registers are not reset by this bit to allow test configurat ions to be written and then not affected by resetting the ctl offset reset value control 0 h 1000 h field bits type description rst 15 rwsc reset 0 b no , normal operation 1 b pr , phy reset lp 14 rw loopback 0 b dl , disables loopback 1 b el , enables loopback ss 13 rw speed selection 0 b 10m , 10 mbit/s 1 b 100m , 100 mbit/s ane 12 rw autonegotiation enable 0 b dan , disables auto-neg 1 b ean , enables auto-neg pd 11 rw power down 0 b no , normal operation 1 b pd , power down iso 10 rw isolate 0 b no , normal operation 1 b iphy , isolate phy from mii ra 9 rwsc restart autonegotiation 1 b ran , restarts auto-neg dm 8 rw duplex mode 0 b ha , half 1 b fu , full ct 7 ro collision test not implemented uzvf 567 uz /3 uz 66 uz $1( uz 3' uz ,62 uzvf 5$ uz '0 ur &7 5hv
data sheet 63 rev. 1.21, 2005-11-08 adm8515/x registers descriptionphy registers port. note: no reset is performed to analogue sections of the port. there is also no physi cal reset to any internal clock synthesisers or the local clock recovery oscillator which will continue to run throughout the reset period. however since the port is restarted and autoneg re-run the process of locking the frequency of the local oscillator (slave) to the reference oscilla tor (master) will be r epeated as it is at the st art of any link initialization process. loopback loop back of transmit data to receive via a path as close to the wire as possible. when set inhibits actual transmission on the wire. speed selection forces speed of phy only when auto-negotiation is disabled. th e default state of this bit will be determined by a power-up configuration pin in this case. otherwise it defaults to 1. auto-neg enable defaults to pin programmed value. when cleared it allows forcing of speed and duplex settings. when set (after being cleared) it causes re-start of auto-neg process. pin programming at power-up allows it to come up disabled and for software to write the desired capabilit y before allowing the firs t negotiation to commence. restart negotiation only has effect when auto-negot iating. restarts state machine. power down has no effect in this device. test mode power down modes may be implemented in other specific modules. isolate puts rmii receive signals in to high impedance state and ignores transmit signals. duplex mode when bit12 is cleared (i.e. autoneg dis abled), this bit forces full duplex (bit = 1) or half duplex (bit = 0) collision test always 0 because collision si gnal is not implemented. status sta offset reset value status 01 h 7849 h field bits type description 100t4 15 ro 100base-t4 not supported 100fd 14 ro 100base-tx full duplex 0 b , phy is not 100base-x full duplex capable 1 b , phy is 100base-x full duplex capable 100hd 13 ro 100base-tx half duplex 0 b , phy is not 100base-x half duplex capable 1 b , phy is 100base-x half duplex capable 10fd 12 ro 10base-t full duplex 0 b , phy is not 10mbit/s full duplex capable 1 b , phy is 10mbit/s full duplex capable 10hd 11 ro 10base-t half duplex 0 b , phy is not 10mbit/s half duplex capable 1 b , phy is 10mbit/s half duplex capable ur 7 ur ) ' ur + ' ur )' ur +' ur 7)' ur 7+' ur 5hv ur 0)3 ur $1& urokvf 5) ur $1$ uroovf /6 urokvf -' ur (&
adm8515/x registers descriptionphy registers data sheet 64 rev. 1.21, 2005-11-08 register 2 and 3 each phy has an identifier, which is assigned to the device.t he identifier contains a total of 32 bits, which consists of the following: 22 bits of a 24bit organizationally unique identifier (oui) for the manufacturer; a 6-bit manufacturer's model number; a 4-bit manufacturer's revision number. for an explanation of how the oui maps to the register, please refe r to ieee 802-1990 clause 5.1 t2fd 10 ro 100base-t2 full duplex not supported t2hd 9 ro 100base-t2 half duplex not supported res 8:7 ro reserved mfp 6 ro mf preamble suppression 0 b , phy cannot accept management frames with preamble suppression 1 b , phy can accept management frames with preamble suppression anc 5 ro auto-negotiate complete 0 b , auto-neg incompleted 1 b , auto-neg completed rf 4 ro/lhsc remote fault this bit will remain set until it is cleared by reading register 1 via management interface. 0 b , no remote fault detected 1 b , remote fault detected ana 3 ro auto-negotiate ability 0 b , phy cannot auto-negotiate 1 b , phy can auto-negotiate ls 2 ro/llsc link status 0 b , link is down 1 b , link is up jd 1 ro/lhsc jabber detect only used in 10base-t mode. reads as 0 in 100base-tx mode 1 b , jabber condition detect ec 0 ro extended capability 0 b , basic register set capabilities only 1 b , extended register capable. field bits type description
data sheet 65 rev. 1.21, 2005-11-08 adm8515/x registers descriptionphy registers phy identifier 1 phy identifier 2 note: this uses the oui of infineon-admtek, device type of 1 and rev 0. phyi1 offset reset value phy identifier 1 2 h 001d h field bits type description phyi 15:0 ro phy identifier[31-16] oui (bits 3-18) phyi2 offset reset value phy identifier 2 3 h 2411 h field bits type description phyi1 15:10 ro phy identifier[15-10] oui (bits 19-24) phyi2 9:4 ro phy identifier[9-4] manufacturer?s model number (bits 5-0) phyi3 3:0 ro phy identifier[3-0] revision number (bits 3-0);register 3, bit 0 is ls bit of phy identifier ur 3+<, ur 3+<, ur 3+<, ur 3+<,
adm8515/x registers descriptionphy registers data sheet 66 rev. 1.21, 2005-11-08 auto-negotiation advertisement ana offset reset value auto-negotiation advertisement 4 h 0001 h field bits type description np 15 rw next page 0 b nnp , device not set to use next page 1 b np , device set to use next page rf 13 rw remote fault 0 b nfd , no fault detected 1 b rf , local remote fault sent to link partner ni 12:11 ro not implemented technology ability bits a7-a6 pau 10 rw pause technology ability bit a5 ni 9 ro not implemented technology ability bit a4 100fd 8 rw 100base-tx full duplex technology ability bit a3 0 b 100nfd , unit is not capable of full duplex 1 b 100fd , unit is capable of full duplex 100hd 7 rw 100base-tx half duplex technology ability bit a2 0 b 100nhd , unit is not capable of half duplex 100base-tx 1 b 100hd , unit is capable of half duplex 10fd 6 rw 10base-t full duplex technology ability bit a1 0 b 10nfd , unit is not capable of full duplex 10base-t 1 b 10fd , unit is capable of full duplex 10base-t 10hd 5 rw 10base-t half duplex technology ability bit a0 0 b 10nhd , unit is not capable of half duplex 10base-t 1 b 10hd , unit is capable of half duplex 10base-t sf 4:0 ro selector field identifies type of message being sent. currently only one value is defined. uz 13 5hv uz 5) ur 1, uz 3$8 ur 1, uz ) ' uz + ' uz )' uz +' ur 6)
data sheet 67 rev. 1.21, 2005-11-08 adm8515/x registers descriptionphy registers auto-negotiation li nk partner ability the register is used to view the ad vertised capabilities of the link partner once auto nego tiation is complete. the contents of this regist er should not be relied upon unless register 1 bit 5 is set (auto negotiation complete). after negotiation this register should contain a copy of the link partner's register 4. all bits are therefore defined in the same way as for register 4.all bits are readable only.this register is used for base page code word only.base page register format auto-negotiation expansion anlpa offset reset value auto-negotiation li nk partner ability 5 h 0000 h field bits type description np 15 ro next page 0 b , base page is requested 1 b , link partner is requesting next page function ack 14 ro acknowledge link partner acknowledgement bit rf 13 ro remote fault link partner is indicating a fault ta 12:5 ro technology ability link partner techno logy ability field. sf 4:0 ro selector field link partner selector field ane offset reset value auto-negotiation expansion 6 h 0004 h field bits type description pdf 4 ro, lh parallel detection fault 0 b nfd , no fault detected 1 b fd , local device para llel detection fault ur 13 ur $&. ur 5) ur 7$ ur 6) 5hv urok 3') ur /313 ur 13$ urok 35 ur /3$1
adm8515/x usb commandget register (vendor specific) single/burst read data sheet 68 rev. 1.21, 2005-11-08 5usb command 5.1 get register (vendor specific) single/burst read the returned total number of registers depends on the length field. 5.2 set register (vendo r specific) burst write ex. write 44 to regindex = 05 h , the transfer will be lpnp 3 ro link partner next page able 0 b nnp , link partner is not next page able 1 b np , link partner is next page able npa 2 ro next page able 0 b , local device is not next page able 1 b , local device is next page able pr 1 ro, lh page received 0 b npr , a new page has not been received 1 b pr , a new page has been received lpan 0 ro link partner auto negotiation able 0 b nan , link partner is not auto negotiation able 1 b an , link partner is auto negotiation able table 27 setup stage bmreq breq wvalue(2b) windex(2b) wlength(2b) c0 f0 0 {regindex[0:7], 00} length table 28 data stage offset0(1b) offset1(1b) offset2(1b) {regindex} {regindex+1) {regindex+2) table 29 setup stage bmreq breq wvalue(2b) windex(2b) wlength(2b) 40 f1 0 {regindex[0:7], 00} length table 30 data stage offset0(1b) offset1(1b) offset2(1b) offset3(1b) {regindex} {regindex+1} {regindex+2} {regindex+3} field bits type description
data sheet 69 rev. 1.21, 2005-11-08 adm8515/x usb commandget status (device) if wlength > 1, more than 1 register is accessed (burst write) and mask is not supported => datastage for 8-byte out transfer appears ex. burst write 20 registers from regindex = 07 h and data from 01 d to 20 d ? data stage 5.3 get status (device) 5.4 get status (interface) table 31 setup stage bmreq breq wvalue(2b) windex(2b) wlength(2b) 40 f1 4400 0500 0100 table 32 setup stage bmreq breq wvalue(2b) windex(2b) wlength(2b) 40 f1 0000 0700 1400 table 33 1st out transfer offset0(1b) offset1(1b) offset2(1b) offset3(1b) offset4(1b) offset5(1b) offset6(1b) offset7(1b) 01 02 03 04 05 06 07 08 table 34 2nd out transfer offset0(1b) offset1(1b) offset2(1b) offset3(1b) offset4(1b) offset5(1b) offset6(1b) offset7(1b) 09 0a 0b 0c 0d 0e 0f 10 table 35 3rd out transfer offset0(1b) offset1(1b) offset2(1b) 11 12 13 table 36 setup stage bmreq breq wvalue(2b) windex(2b) wlength l(1b) wlength h(1b) 8000020 table 37 data stage d[15:2] d[1]: remote wakeup d[0]:self powered 0 register of remote_wakeup 1 table 38 setup stage bmreq breq wvalue(2b) windex(2b) wlength l(1b) wlength h(1b) 8100020
adm8515/x usb commandget status (ep1) bulk in data sheet 70 rev. 1.21, 2005-11-08 5.5 get status (ep1) bulk in 5.6 get status (ep2) bulk out 5.7 get status (ep3) interrupt in table 39 data stage d[15:0] 0 table 40 setup stage bmreq breq wvalue(2b) windex l(1b) windex h(1b) wlength l(1b) wlength h(1b) 8200810020 table 41 data stage d[15:1] d[0]: halt 0 register of ep1_halt table 42 setup stage bmreq breq wvalue(2b) windex l(1b) windex h(1b) wlength l(1b) wlength h(1b) 8200020020 table 43 data stage d[15:1] d[0]: halt 0 register of ep2_halt table 44 setup stage bmreq breq wvalue(2b) windex l(1b) windex h(1b) wlength l(1b) wlength h(1b) 8200830020 table 45 data stage d[15:1] d[0]: halt 0 register of ep3_halt
data sheet 71 rev. 1.21, 2005-11-08 adm8515/x usb commandget descriptor (device) total 18-byte 5.8 get descriptor (device) total 18-byte default value *product id = 8515 h *vendor id = 07a6 h 5.9 get descriptor (config uration) total 39-byte ? data stage table 46 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength l(1b) wlength h(1b) 80 6 01 00 0 length low length high table 47 data stage: wlength field specifies the total byte count to return offset 0 offset 1 (type) offset 2 (usb release no. l) offset 3 (usb release no. h) offset 4 (class code) offset 5 (sub class code) offset 6 (protocol) offset 7 (ep0 maxpktsize) 12(1 b )01(1 b ) 10/00(1 b ) 01/02(1 b )ff(1 b )ff(1 b )00(1 b ) 8/64(1 b ) table 48 *8/64 := usb 1.1/2.0 offset 8 (vendor id) low offset 9 (vendor id) high offset 10 (productid) low offset 11 (productid) high offset 12 (releaseid low) (1 b )(1 b )(1 b )(1 b )01(1 b ) table 49 *8/64 := usb 1.1/2.0 offset 16 (serial no.) offset 17 (no. of config) offset 13 (releaseid high) offset 14 (m anufacture) offset 15 (product) 03(1 b )01(1 b ) 01(1 b )01(1 b )02(1 b ) table 50 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength l(1b) wlength h(1b) 80 6 02 00 0 length low length high table 51 configuration descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (totallength) low offset 3 (totallength) high offset 4 (numinterface) 09(1 b )02(1 b ) 27(1 b )00(1 b )01(1 b )
adm8515/x usb commandget descriptor (string) index 0, languageid code data sheet 72 rev. 1.21, 2005-11-08 5.10 get descriptor (string) index 0, languageid code table 52 configuration descriptor offset 8 (maxpower) offset 5 (confgvalue) offset 6 (stringindex) offset 7 (attribute) max_pwr(1 b )01(1 b )00(1 b )1? b 1, powermode, remote wakeup, 5? h 00(1 b ) table 53 interface 0 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (interface num) offset 3 (altinterfa ce) offset 4 (numep) offset 5 (intfclass) offset 6 (intfsubcl ass) offset 7 (intfproto col) offset 8 (stringind ex) 09(1 b )04(1 b )00(1 b ) 00(1 b )03(1 b )ff(1 b ) ff(1 b ) 00(1 b )00(1 b ) table 54 ep1 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 5 (maxpktsize) high offset 6 (interval) 07(1 b )05(1 b )81(1 b )02(1 b ) bulk 40 h /00 h (1 b )00 h /02 h (1 b )00(1 b ) table 55 ep2 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 4 (maxpktsize) high offset 6 (interval) 07(1 b ) 05(1 b ) 02(1 b ) 02(1 b ) bulk 40 h /00 h (1 b ) 00h/02h(1 b )00(1 b ) table 56 ep3 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 5 (maxpktsize) high offset 6 (interval) 07(1 b )05(1 b )83(1 b ) 03(1 b ) interrupt 08(1 b )00(1 b ) ep3_interval(1 b ) table 57 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength low(1b) wlength high(1b) 80 06 00 03 0000 length low length high table 58 data stage offset0 (length) offset1 (dscrtype) offset2 (languageid) l offset3 (languageid) h 04(1 b )03(1 b )09(1 b )04(1 b )
data sheet 73 rev. 1.21, 2005-11-08 adm8515/x usb commandget descriptor (string) index 1, manufacture 5.11 get descriptor (stri ng) index 1, manufacture 5.12 get descriptor (str ing) index 2, product 5.13 get descriptor (stri ng) index 3, serial no. 5.14 get configuration table 59 setup stage bmreq breq wvalue l(1b) wvalu e h(1b) windex (2b) wlength low(1b) wlength high(1b) 80 06 01 03 0904 length low length high table 60 data stage offset0 (length) offset1 (dscrtype) length(1 b b 03(1b) string table 61 setup stage bmreq breq wvalue l(1b) wvalu e h(1b) windex (2b) wlength low(1b) wlength high(1b) 80 06 02 03 0904 length low length high table 62 data stage offset 0 (length) offset 1 (dscrtype) length(1 b )03(1 b )string table 63 setup stage bmreq breq wvalue l(1b) wvalu e h(1b) windex (2b) wlength low(1b) wlength high(1b) 80 06 03 03 0904 length low length high table 64 data stage offset 0 (length) offset 1 (dscrtype) length(1 b )03(1 b )string table 65 setup stage bmreq breq wvalue(2b) windex(2b) wlength low(1b) wlength high(1b) 80080010
adm8515/x usb commandget interface data sheet 74 rev. 1.21, 2005-11-08 5.15 get interface 5.16 get descriptor (device qualifier) 5.17 get descriptor (o ther speed configur ation) total 39-byte ? data stage table 66 data stage d[7:1] d[0]: cfg_value 0 register of cfg value table 67 setup stage bmreq breq wvalue(2b) windex(2b) wlength low(1b) wlength high(1b) 810a0010 table 68 data stage offset0 (altintf) (1b) 00 table 69 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength l(1b) wlength h(1b) 80 6 06 00 0 length low length high table 70 data stage offset 0 (length) offset 1 (dscrtype) offset 2 (bcdusb) offset 4 (class) offset 5 (subclass) 0a(1 b )06(1 b ) 0200 h (2 b )ff h (1 b )ff h (1 b ) table 71 data stage offset 9 (reserved) offset 6 (deviceprotocal) offset 7 (maxpktsizefor other speed ) offset 8 (no of other speed configuration) 00(1 b )00 h (1 b )08 h (1 b )01 h (1 b ) table 72 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength l(1b) wlength h(1b) 80 6 07 00 0 length low length high
data sheet 75 rev. 1.21, 2005-11-08 adm8515/x usb commandclear feature (device) remote wakeup 5.18 clear feature (d evice) remote wakeup table 73 configuration descriptor offset 0 (length) offset 1 (dscrtype) offset 2( totallength) low offset 3 (totallength) high offset 4 (numinterface) 09(1 b )07(1 b ) 27(1 b )00(1 b )01(1 b ) table 74 configuration descriptor offset 8 (maxpower) offset 5 (confgvalue) offset 6 (stringindex) offset 7 (attribute) max_pwr(1 b )01(1 b )00(1 b )1? b 1, powermode, remote wakeup, 5? h 00(1 b ) table 75 interface 0 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (interface num) offset 3 (altinterfa ce) offset 4 (numep) offset 5 (intfclass) offset 6( intfsubcl ass) offset 7 (intfproto col) offset 8 (stringind ex) 09(1 b )04(1 b )00(1 b ) 00(1 b )03(1 b ) ff(1 b )ff(1 b )00(1 b )00(1 b ) table 76 ep1 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 5( maxpktsize) high offset 6 (interval) 07(1 b )05(1 b )81(1 b ) 02(1 b ) bulk 40 h (1 b )00 h (1 b ) 00(1 b ) table 77 ep2 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 4 (maxpktsize) high offset 6 (interval) 07(1 b )05(1 b )02(1 b ) 02(1 b ) bulk 40 h (1 b )00 h (1 b ) 00(1 b ) table 78 ep3 descriptor offset 0 (length) offset 1 (dscrtype) offset 2 (epaddr) offset 3 (attribute) offset 4 (maxpktsize) low offset 5 (maxpktsize) high offset 6 (interval) 07(1 b )05(1 b )83(1 b ) 03(1 b ) interrupt 08(1 b ) 00(1 b ) ep3_interval( 1 b ) table 79 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength(2b) 00 01 01 00 0 0
adm8515/x usb commandset feature (device) remote wakeup data sheet 76 rev. 1.21, 2005-11-08 5.19 set feature (devi ce) remote wakeup 5.20 clear feature (ep 0, 1, 2, 3) halt 5.21 set feature (ep 0, 1 ,2, 3) halt device should respond st all if endpoint halt. 5.22 set feature (test mode) test selector : 00 h = reserved 01 h = test_j 02 h = test_k 03 h = test_se0_nak others = reserved table 80 setup stage bmreq breq wvalue l(1b) wvalue h(1b) windex(2b) wlength(2b) 00 03 01 00 0 0 table 81 setup stage bmreq breq wvalue(2b) windex l(1b) windex l(2b) wlength(2b) 02 01 0000 ep no 00 0 table 82 setup stage bmreq breq wvalue(2b) windex h( 1b) windex h(2b) wlength(2b) 02 03 0000 ep no 00 0 table 83 setup stage bmreq breq wvalue(2b) windex h( 1b) windex h(2b) wlength(2b) 02 03 0002 test selector 00 0
data sheet 77 rev. 1.21, 2005-11-08 adm8515/x electrical characteristics 6 electrical characteristics 6.1 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 6.2 operating condition 6.3 dc specifications 6.3.1 usb interface dc specification table 84 absolute maximum rating parameter symbol values unit note / test condition min. typ. max. supply voltage v dd -0.3 ? 3.6 v ? input voltage v in -0.5 ? v dd +0.5 v ? output voltage v out -0.5 ? v dd +0.5 v ? storage temperature t stg -65 ? 150 c? ambient temperature t amb 0?70 w? esd rating v esd ??2000v? table 85 operating condition parameter symbol values unit note / test condition min. typ. max. supply voltage v dd 3.0 ? 3.6 v ? usb bus supply voltage 5v dd 4.4 ? 5.25 v ? table 86 usb interface dc specification parameter symbol values unit note / test condition min. typ. max. input high voltage v ih 2.0 ? ? v ? input low voltage v il ??0.8v? differential inpu t sensitivity v di 0.2 ? ? v ? differential common mode range v cm 0.8? 2.5v?
data sheet 78 rev. 1.21, 2005-11-08 adm8515/x electrical characteristics 6.3.2 eeprom interface dc specification recommended operating conditions: 6.3.3 gpio interfa ce dc specification 6.4 timing 6.4.1 reset timing adm8515/x can be reset either by hardware, software or usb reset. ? a hardware reset is accomplished by asserting the rst# pin after powering up the device. it should have a duration of at least 100 ms to ensure the external 12 mh z crystal is in stable and correct frequency. all registers will be reset to default values. ? a software reset is accomplished by setting the reset bit (bit 3) of the ethernet control register (address 01 h ). this software reset will reset all register s to default values. output high voltage v ch 2.8? 3.6v? output low voltage v ol 0.0? 0.3v? output signal crossover voltage v crs 1.3? 2.0v? table 87 eeprom interfa ce dc specification parameter symbol values unit note / test condition min. typ. max. input high voltage v ih 1.8? 5.5v? input low voltage v il -0.5 ? 1.0 v ? input leakage current i i -1 ? +1 a0< v in < v cc output high voltage v oh v cc -0.2 ? ? v i oh = -10 a output low voltage v ol ??0.2v i ol = 10 a input pin capacitance c in ??5pf? table 88 gpio interface dc specification parameter symbol values unit note / test condition min. typ. max. input high voltage v ih 1.8? 5.5v? input low voltage v il -0.5 ? 1.0 v ? input leakage current i i 1 na ? 1 a v in 3.3 v or 0 v output high voltage v oh 2.4 ? ? v ? output low voltage v ol ??0.4v? input pin capacitance c in ? ? 5.64 pf ? table 86 usb interface dc specification (cont?d) parameter symbol values unit note / test condition min. typ. max.
data sheet 79 rev. 1.21, 2005-11-08 adm8515/x electrical characteristics ? when adm8515/x sees an se0 on usb bus for more th an 2.5 s. this usb reset will reset all registers to default values. 6.4.2 eeprom interface timing figure 6 eeprom interface timing table 89 eeprom interface timing parameter symbol values unit note / test condition min. typ. max. eesk clock frequency t eesk 0?1mhz? eecs setup time to eesk t eecss 0.2 ? ? s? eecs hold time from eesk t eecsh 0??ns? eedo hold time from eesk t eedoh 70 ? ? ns ? eedo output delay to ?1? or ?0? t eedop ??2 s? eedi setup time to eesk t eedis 0.4 ? ? s? eedi hold time from eesk t eedih 0.4 ? ? s?
data sheet 80 rev. 1.21, 2005-11-08 adm8515/x electrical characteristics 6.4.3 mii interface timing figure 7 transmit signal timing relationships at the mii figure 8 received signal timi ng relations at the mii
data sheet 81 rev. 1.21, 2005-11-08 adm8515/x electrical characteristics figure 9 mdio sourced by sta figure 10 mdio sourced by phy
data sheet 82 rev. 1.21, 2005-11-08 adm8515/x packaging 7 packaging package outline of adm8515/x figure 11 p-lqfp-100-1 (plastic low profile quad flat package) note: dimensions in mm
data sheet 83 rev. 1.21, 2005-11-08 adm8515/x packaging table 90 dimensions for 100 pin lqfp package symbol millimeter (mm) inch min . typ. max. min. typ. max. a ? ?1.60? ?0.063 a 1 0.05 ? 0.15 0.002 ? 0.006 a 2 1.35 1.40 1.45 0.053 0.005 0.057 d 16.00 bsc. 0.630 bsc. d 1 14.00 bsc 0.551 bsc. e 16.00 bsc 0.630 bsc. e 1 14.00 bsc 0.551 bsc. r 2 0.08 ? 0.20 0.003 ? 0.008 r 1 0.08 ? ? 0.003 ? ? 0 3.5 7 0 3.5 7 1 0 ? ? 0 ? ? 2 11 12 13 11 12 13 3 11 12 13 11 12 13 c 0.09 ? 0.20 0.004 ? 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref. 0.039 ref. s 0.20 ? ? 0.008 ? ? b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc. 0.020 bsc. d 2 12.00 0.472 e 2 12.00 0.472 tolerance of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
data sheet 84 rev. 1.21, 2005-11-08 adm8515/x appendix 8appendix 8.1 appendix 1 eeprom content & example the eeprom contents from offset 0 to offset5 is ?ff_ ff_ff_ff_ff_ff?, the eepr om isn?t programmed correctly. the default values for every field are used in stead of loading from eeprom. offset (byte) field description 00 node_id0 the 1st byte of ethernet node id. 01 node_id1 the 2nd byte of ethernet node id. 02 node_id2 the 3rd byte of ethernet node id. 03 node_id3 the 4th byte of ethernet node id. 04 node_id4 the 5th byte of ethernet node id. 05 node_id5 the 6th byte of ethernet node id. 06-07 signature 0x8515 08 max_pwr the maximum usb power consumption. 09 ep3_interval the polling interval for en dpoint 3. if this value is 0, ep3 is disabled. 0a[0] reserved 0a[1] usb_sel 0a[1] = 0: select external usb 2.0 transceiver oa[1] = 1: select internal usb 2.0 transceiver. 0a[4:2] phy mode 0a[4:2] = 000: tri-state mii pins 0a[6] bus power selection 0a[6] = 0: bus power 0a[6] = 1: self power 0a[7] remote wake up 0a[7] = 0: with wakeup cap 0a[7] = 1: without wakeup cap 0b[5:0] reserved 0b[7:6] led mode refer to pin description 0c languageid_lo the low byte of language id. 0d languageid_hi the high byte of language id. 0e-0f reserved 10 manuid_lo the low byte of manufacture id. 11 manuid_hi the high byte of manufacture id. 12 proid_lo the low byte of product id. 13 proid_hi the high byte of product id. 14 manu_str_len the length for manufacture string. 15 manu_str_offset the word offset address of manufacture string. 16 pro_str_len the length for product string. 17 pro_str_offset the word offset address of product string. 18 seri_str_len the length for serial number string. 19 seri_str_offset the word offset address of serial number string.
data sheet 85 rev. 1.21, 2005-11-08 adm8515/x appendix table 91 example offset (byte) value 0000 h 00 00 e8 00 02 2c 00 00 0008 h 50 01 02 00 09 04 00 00 0010 h a6 07 15 85 0e 10 2a 20 0018 h 0a 38 00 00 00 00 00 00 0020 h 0e 03 41 00 44 00 4d 00 0028 h 74 00 65 00 6b 00 00 00 0030 h 1e 00 55 00 53 00 42 00 0038 h 20 00 31 00 30 00 2f 00 0040 h 2a 03 55 00 53 00 42 00 0048 h 20 00 54 00 6f 00 20 00 0050 h 4c 00 41 00 4e 00 20 00 0058 h 43 00 6f 00 6e 00 76 00 0060 h 65 00 72 00 74 00 65 00 0068 h 72 00 00 00 00 00 00 00 0070 h 0a 03 30 00 30 00 30 00 0078 h 31 00 00 00 00 00 00 00 offset (byte) value description 00-05 00_00_e8_10_46_02 nic node id 08 50 maximum power 160 ma 09 01 interrupt endpoint 3 polling interval 1ms 0a 02 isochronous endpoint disable, select internal usb transceiver, use bus power. use internal ethernet phy, wake on lan enable 0c-0d 0904 language id 0409 10-11 a607 manufacture id 07a6 12-13 8515 product id 8515 14 0e manufacture string length 0e bytes 15 10 manufacture string starts from word offset 10 h , thus byte offset 20 h . 16 1e product string length 1e bytes 17 18 product string starts from word offset 18 h , thus byte offset 30 h . 18 0a serial number string length 0a bytes 19 38 serial number string starts from word offset 38 h , thus byte offset 70 h . 20-2e 0e 03 41 00 44 00 4d 00 74 00 65 00 6b 00 0e:descriptor size 14 bytes 03: string descriptor 41........: unicode encoded string
data sheet 86 rev. 1.21, 2005-11-08 adm8515/x appendix 30-4e 1e 03 55 00 53 00 42 0020 00................ 1e:descriptor size 30 bytes 03: string descriptor 55........: unicode encoded string 50-5a 0a 03 30 00 30 00 30 0031 00 0a: descriptor size 10 bytes 03: string descriptor 30........: unicode encoded string offset (byte) value description
data sheet 87 rev. 1.21, 2005-11-08 adm8515/x terminology a ack acknowledge b bist built in self test c col collision crc cyclic redundancy check crs carrier sense d dc direct current dm differential minus dp differential plus e ep end point esd electro static discharge f fifo first in first out flp first link pulse g gpio general purpose input output h hw hardware i i/o input/output ia information appliance isi inter-symbol interface l lan local area network led light emitting diode lh latch high lqfp low profile quad flat package ls least significant bit m mac media access controller mdc management data clock mdio management data input/output mfg manufacture program mii media independent interface n nak not acknowledge nlp normal link pulse
data sheet 88 rev. 1.21, 2005-11-08 adm8515/x o os operating system oui organizationally unique identifier p ppower pin phy physical layer pie parallel interface engine pmd physical medium dependent r rx receive rxclk receive clock rxd receive data rxdv receive data valid s sqe signal quality error sw software t tx transmit txclk transmit clock txd transmit data txin transmit input negative txip transmit input positive u usb universal serial bus utmi usb 2.0 transceiver macrocell interface v vdd voltage vin voltage in vout voltage out w wan wide area network x xcvr transceiver xdsl a/s/v dsl
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